1. Technical Field
The present application relates to analog voltage generation, and more particularly to low-power generation of many different desired voltages on a nonvolatile memory integrated circuit.
2. Related Art
Many portable electronic systems are critically limited by battery life. For example, users do not like heavy cell phones, but users also do not like their cell phones to run out of power and shut: down. One way to improve battery life is to increase the energy efficiency of the electronics components in the portable system.
As the constraints of low-power integrated circuits have steadily become tighter, the pressure on voltage management has similarly tightened. Power consumption issues, as well as the normal progress of voltage scaling, push designers toward tighter management of voltages on-chip. Accurate power-valid thresholds, or voltage margins which are dynamically determined in a multi-interface chip, are examples of this.
The availability of power island design techniques also means that reference voltages for the particular needs of a particular power island may be demanded.
Modern nonvolatile memory development is turning into one of the most rapidly advancing areas in the semiconductor industry. Memory cell technology itself continues to advance, even within the general areas However, since the transistor operations are inherently not digital, a variety of reference levels are likely to be needed by memory designs. Thus the capability for generation of secondary analog voltages on chip is important.
The bandgap voltage reference circuit is one of the mainstays of analog electronics, and provides a very reliable on-chip reference. However, this circuit topology, in its many variations, is generally limited to one specific output voltage, and consumes power. It is therefore generally preferable not to use more than one bandgap reference circuit per chip.
The case of a low-power nonvolatile memory module is the convergence of the above requirements. Many different voltages must be made available on chip, and yet static power consumption in the various voltage generation stages is extremely undesirable.
As shown in FIG. 1, a current source, mirrored from elsewhere on chip, can be combined with a voltage-drop or ohmic element to give a reference voltage output. However, this approach has a constant power loss of the regulated voltage times the reference current squared.
A pending U.S. patent application (U.S. Pat. No. 11/497,465, filed Jul. 31, 2006, titled “Hybrid Charge Pump Regulation”) by the same inventor noted the advantages of a capacitive divider in the feedback loop of a voltage generator circuit. In this example, as illustrated in FIG. 2, the op amp shown at the right of the diagram drives the charge pump shown at the top left to maintain the output at a level which is equal to the reference voltage Vref times the capacitive ratio.
In the circuit of FIG. 2, the “div” node is pulled down to ground during the initial phase. After the initial phase the op amp drives the charge pump to make node div equal to Vref, so the output voltage is driven towards Vref times the capacitor ratio (C1+C2)/C2. Note that the output voltage is directly dependent on the capacitor ratio, so process variation, geometric effects, and parasitic capacitance effects can all affect the output voltage.
The present application discloses a significant improvement to that circuit.